Algorithms for the scaling toward nanometer VLSI physical synthesis

Algorithms for the Scaling Toward Nanometer VLSI Physical Synthesis. (December 2005) Chin Ngai Sze, B.Eng., The Chinese University of Hong Kong; M.Phil., The Chinese University of Hong Kong Chair of Advisory Committee: Dr. Jiang Hu Along the history of Very Large Scale Integration (VLSI), we have successfully scaled down the size of transistors, scaled up the speed of integrated circuits (IC) and the number of transistors in a chip these are just a few examples of our achievement in VLSI scaling. It is projected to enter the nanometer ( ) scale era in the nearest future. At the same time, the scaling has imposed new challenges to physical synthesis. Among all the challenges, this thesis focuses on the following problems: Increasingly domination of interconnect delay leads to a need in interconnect-centric design flows; Different design stages (e.g. floorplanning, placement and global routing) have unmatched timing estimation, which brings difficulty in timing closure; More and more VLSI circuits are designed in architectural styles, which require a new set of algorithms. The paper consists of two parts, each of which focuses on several specific problems in VLSI physical synthesis when facing the new challenges. Part-1 Place and route aware buffer Steiner tree construction Efficient techniques are presented for the problem of buffered interconnect tree construction under blockage and routing congestion constraint. This part also contains